Array IC Packaging Rising to Meet the Bandwidth Challenge

YouTube, Facebook, Twitter, smart phone apps, and so many other Internet uses are driving up the bandwidth requirements from our electronic devices at a tremendous pace.  Sharing photos now a days does not involve passing around a photo album in the living room.  Today photos and videos are shared electronically nearly the instant they are taken as they are loaded up on Facebook and other social media, often from small handheld electronic gadgets such as tablets and smart phones.

Smart phones are also changing the way we do business.  Small businesses away from electrical outlets can check competitor pricing on goods being sold even in third world countries and charge a sale using an attached Square device.  Medical doctors can now add an attachment to their smart phones to help with diagnosis of medical problems, which has the potential to revolutionize the medical industry into the portable realm.  This will not only reduce medical costs, but will also expand medical coverage into areas of the world which otherwise would not reap the benefits of modern medicine.

This use of the Internet is demanding more and more of the electronics within the electronic gadget, including the IC package which connects the IC to the board and the other chips.  Small size, high performance, lower power requirements, and reduced battery usage are all hot button issues which are influenced more and more by IC packaging.

Array IC packaging, in which the package I/O are beneath the package in an array layout rather than just at the perimeter as with traditional leadframe packages, allow for the higher density needed to meet those issues in order to keep pace with the advancing speed of the IC device and demand for bandwidth capability.

The IC package is the determining factor in the following:

  • Footprint or space consumed on the printed circuit board (PCB).
  • Physical length and thus speed it takes for the electron to leave the IC to travel to other ICs and the PCB.
  • Influences the battery usage and power requirements.

Array packages include the PGA, BGA, FBGA, Fan-in QFN, and Fan-out  and Fan-in WLPs.  The pin grid array, or PGA, is a through-hole package with pins which attach it to the PCB.  The other packages have more options.

BGA / FBGA

BGAs and FBGAs do not have to have solder balls beneath the package substrate; the package can have just land pads or columns instead of balls for the second level interconnection, which connects the package to the printed circuit board.  In the absence of solder balls, where land pads form the connection to the PCB, the package is considered to be a land grid array  (LGA).  If the initial form factor is in the fine-pitch, close to die size category, as it is with the FBGA, the land package is a FLGA.

These land packages are shorter in the “z” dimension, making them ideal in ultra-thin products where the overhead space for a package is at a minimum.  However, in the absence of the self-centering nature of the solder balls, package placement on the PCB must be more accurate, thus more expensive with slower throughput than their balled counterparts.

Packages with column attachment to the PCB are known as column grid arrays (CGAs), which allow for a finer pitch than solder balls, and more interconnection density.  These are more expensive to produce than the BGA or LGA package solutions.

Fan-In QFN Package Solutions

The quad flatpack no-lead, or QFN, is a newer package introduced onto the market in 2008.  It was designed to reach into markets with a lower I/O count than the larger I/O count QFP, and capture the lower end of that market.  It is close to die size, thus considered a chip scale package, or CSP.

A new twist has been added to the QFN to add additional rows to this leadframe package, turning it into a leadframe version of an array package, and one that can reach even further into the market which would otherwise be covered by the larger QFP.  Additional rows are “fanned in” from the traditional perimeter-style leadframe, making this package unique.

Two to three rows of leads are created to form a perimeter array pattern on the underside of the package.  The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multi-row, array-patterned package solution with a hole in the center, or fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. The resulting package is a high-density, leadframe array package.

Demand for both the traditional QFN and Fan-in QFNs are on the rise, see in Table 1.

Table 1 Fan-In QFN

 

2012

2013

2014

2015

2016

2017

QFN Percentage of Total IC Packages

12.4%

12.7%

13.2%

13.8%

14.4%

14.8%

Growth Rate of Fan-In QFN and QFP

184.5%

15.4%

25.9%

11.9%

10.5%

9.9%

As a Percentage of Total QFN Market

3.4%

3.6%

4.1%

4.2%

4.3%

4.3%

 

Fan-Out WLPs

Wafer Level Packages, or WLPs, are the smallest package solution on the market, being die sized.  This unique package is formed while the die are still part of an uncut wafer, the only package to be created or assembled in this manner.  All the solder balls or bumps then must fit beneath the die itself, which limits the number of I/O which is on these packages.

Reconfigured or Fan-out wafer-level packages were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection, enlarging the “face” of the die. This allows for a larger surface on which to extend a redistribution layer (RDL), thus allowing for far more I/Os than would be possible on the original smaller surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board.  All these processes are done on an uncut wafer, so that manufacturing efficiencies are maximized.

Like the Fan-in QFN, demand for both the WLP and the Fan-out WLP are on the rise, shown in Table 2.

Table 2 Fan-Out WLP

2012

2013

2014

2015

2016

2017

WLP Percent of WW IC Packaging Market

5.3%

5.5%

5.7%

5.9%

6.0%

6.1%

Growth Rate for Fan-out WLPs

60.1%

19.0%

17.0%

16.6%

6.8%

6.1%

Fan-out WLP Percent of total WLPs

9.5%

10.1%

10.8%

11.5%

11.7%

11.6%

Total Array IC Packaging

The total of the array packages, including PGA, BGA, FBGA, Fan-in QFN, and Fan-out  and Fan-in WLPs, was 27.5 percent of the total IC packages (less DCA and accounts for multi-die packages) assembled in 2012. The compound annual growth rate (GAGR) of ICs is 5.5 percent for the years through 2017.  With this expanding number of ICs being produced each year, the percent of array IC packages being assembled will increase to 29 percent in 2017, thus they are growing at a faster rate than perimeter outline packages.

More Information

More information on these package solutions can be found in New Venture Research’s newly published report, Array IC Packaging Market. To find out more about this and other reports on IC packaging, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: 1-(408) 244-1100, or Sandra Winkler at slwinkler@newventureresearch.com, Tel: 1-(650) 299-9365.  See newventureresearch.com for information on all the reports from NVR.

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