Having all the functionality of a video recorder, camera, cell phone, computer, and the ability to have Internet access all in one device which fits in one’s pocket is an amazing feat.

Increasingly it is the IC package which is aiding the transformation in the way we communicate, listen to music, gather data, address our medical needs, and perform our everyday business needs.  The report, The Multi-Component IC Packaging Market, 2014 Edition, covers these important IC package technologies, including stacked packaging , through via technology, 2.5-D and 3-D technologies, and system in package, or SiP.

Complex multi-component IC packages have added a new dimension to high speed and small form factor.   The through via technology, also knows as TSV, or through silicon via technology, is an innovative method of connecting the die in these packages in which the die are vertically stacked, and will have the ability to usher in a host of new products with even higher bandwidth capabilities, thus being a “game changer” for the industry.  This technology will allow for higher bandwidth, smaller form factor, lower battery consumption, and higher speed.  More will be able to be accomplished with smaller handheld devices, including medical diagnostics which can be performed anywhere Internet or RF capability is available.  The list is endless of what may become…

For more information, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: (408) 244-1100, or Sandra Winkler at (650) 299-9365.

YouTube, Facebook, Twitter, smart phone apps, and so many other Internet uses are driving up the bandwidth requirements from our electronic devices at a tremendous pace.  Sharing photos now a days does not involve passing around a photo album in the living room.  Today photos and videos are shared electronically nearly the instant they are taken as they are loaded up on Facebook and other social media, often from small handheld electronic gadgets such as tablets and smart phones.

Smart phones are also changing the way we do business.  Small businesses away from electrical outlets can check competitor pricing on goods being sold even in third world countries and charge a sale using an attached Square device.  Medical doctors can now add an attachment to their smart phones to help with diagnosis of medical problems, which has the potential to revolutionize the medical industry into the portable realm.  This will not only reduce medical costs, but will also expand medical coverage into areas of the world which otherwise would not reap the benefits of modern medicine.

This use of the Internet is demanding more and more of the electronics within the electronic gadget, including the IC package which connects the IC to the board and the other chips.  Small size, high performance, lower power requirements, and reduced battery usage are all hot button issues which are influenced more and more by IC packaging.

Array IC packaging, in which the package I/O are beneath the package in an array layout rather than just at the perimeter as with traditional leadframe packages, allow for the higher density needed to meet those issues in order to keep pace with the advancing speed of the IC device and demand for bandwidth capability.

The IC package is the determining factor in the following:

• Footprint or space consumed on the printed circuit board (PCB).
• Physical length and thus speed it takes for the electron to leave the IC to travel to other ICs and the PCB.
• Influences the battery usage and power requirements.

Array packages include the PGA, BGA, FBGA, Fan-in QFN, and Fan-out  and Fan-in WLPs.  The pin grid array, or PGA, is a through-hole package with pins which attach it to the PCB.  The other packages have more options.

BGA / FBGA

BGAs and FBGAs do not have to have solder balls beneath the package substrate; the package can have just land pads or columns instead of balls for the second level interconnection, which connects the package to the printed circuit board.  In the absence of solder balls, where land pads form the connection to the PCB, the package is considered to be a land grid array  (LGA).  If the initial form factor is in the fine-pitch, close to die size category, as it is with the FBGA, the land package is a FLGA.

These land packages are shorter in the “z” dimension, making them ideal in ultra-thin products where the overhead space for a package is at a minimum.  However, in the absence of the self-centering nature of the solder balls, package placement on the PCB must be more accurate, thus more expensive with slower throughput than their balled counterparts.

Packages with column attachment to the PCB are known as column grid arrays (CGAs), which allow for a finer pitch than solder balls, and more interconnection density.  These are more expensive to produce than the BGA or LGA package solutions.

Fan-In QFN Package Solutions

The quad flatpack no-lead, or QFN, is a newer package introduced onto the market in 2008.  It was designed to reach into markets with a lower I/O count than the larger I/O count QFP, and capture the lower end of that market.  It is close to die size, thus considered a chip scale package, or CSP.

A new twist has been added to the QFN to add additional rows to this leadframe package, turning it into a leadframe version of an array package, and one that can reach even further into the market which would otherwise be covered by the larger QFP.  Additional rows are “fanned in” from the traditional perimeter-style leadframe, making this package unique.

Two to three rows of leads are created to form a perimeter array pattern on the underside of the package.  The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multi-row, array-patterned package solution with a hole in the center, or fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. The resulting package is a high-density, leadframe array package.

Demand for both the traditional QFN and Fan-in QFNs are on the rise, see in Table 1.

Table 1 Fan-In QFN

Fan-Out WLPs

Wafer Level Packages, or WLPs, are the smallest package solution on the market, being die sized.  This unique package is formed while the die are still part of an uncut wafer, the only package to be created or assembled in this manner.  All the solder balls or bumps then must fit beneath the die itself, which limits the number of I/O which is on these packages.

Reconfigured or Fan-out wafer-level packages were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection, enlarging the “face” of the die. This allows for a larger surface on which to extend a redistribution layer (RDL), thus allowing for far more I/Os than would be possible on the original smaller surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board.  All these processes are done on an uncut wafer, so that manufacturing efficiencies are maximized.

Like the Fan-in QFN, demand for both the WLP and the Fan-out WLP are on the rise, shown in Table 2.

Table 2 Fan-Out WLP

Total Array IC Packaging

The total of the array packages, including PGA, BGA, FBGA, Fan-in QFN, and Fan-out  and Fan-in WLPs, was 27.5 percent of the total IC packages (less DCA and accounts for multi-die packages) assembled in 2012. The compound annual growth rate (GAGR) of ICs is 5.5 percent for the years through 2017.  With this expanding number of ICs being produced each year, the percent of array IC packages being assembled will increase to 29 percent in 2017, thus they are growing at a faster rate than perimeter outline packages.

More Information

More information on these package solutions can be found in New Venture Research’s newly published report, Array IC Packaging Market. To find out more about this and other reports on IC packaging, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: 1-(408) 244-1100, or Sandra Winkler at slwinkler@newventureresearch.com, Tel: 1-(650) 299-9365.  See newventureresearch.com for information on all the reports from NVR.

Small form factor, high speed and performance, and high bandwidth capability with low battery consumption are desired traits for many packaging solutions for integrated circuits (ICs).  High demand for handheld and high performance electronic devices is the driving factor behind the IC packaging needs.

IC packages with an array layout, as opposed to a perimeter layout, allow for more I/O density in a smaller form factor, meeting the needs outlined above.  Thus demand for array packages is on the rise, as additional I/O connections are fit beneath the package than traditional leadframe packages, providing them with form factor benefits.  BGA and FBGA package solutions also reach into I/O levels which are unreachable by traditional leadframe packages, as the substrate can be enlarged to fit a large number of solder balls, land pads, or columns beneath it to attach to the PCB.

Array packages include the PGA, BGA, FBGA, Fan-in QFN, and Fan-out WLPs.  The pin grid array, or PGA, is a through-hole package with pins which attach it to the PCB.  The other packages have more options.

BGA / FBGA

Ball grid arrays (BGAs) and their smaller cousins, fine-pitched ball grid arrays (FBGAs) generally have solder balls on the underside of the substrate for attachment to the printed circuit board (PCB).  The balls provide a self-centering effect during reflow, as well as a standoff for flexibility during electrical surges.

Removing these solder balls makes these packages land grid arrays, or LGAs, which allow for a shorter package in the “z” dimension.  This is important in thinner products, although the package placement to the PCB must be of greater accuracy and thus have a slower throughput.

Columns can take the place of solder balls, which allow for finer pitch and greater density of I/O connections.  These are known as column grid arrays, or CGAs.  These are more expensive to produce than the BGA or LGA package solutions.

The forecasts of each of these segments are provided in New Venture Research’s newly published report, The Array IC Packaging Market, 2013 Edition.

Fan-In QFN Package Solutions

The quad flatpack no-lead, or QFN, is a newer package introduced onto the market in 2008.  A new twist has been added to the QFN to add additional rows to this leadframe package, turning it into a leadframe version of an array package, and one that can reach even further into the market which would otherwise be covered by the larger QFP.  Additional rows are “fanned in” from the traditional perimeter-style leadframe, making this package unique.

Demand for both the traditional QFN and Fan-in QFNs are on the rise, shown in Table 1.

Table 1 Fan-In QFN

Fan-Out WLPs

Wafer Level Packages, or WLPs, are the smallest package solution on the market, being die sized.  This unique package is formed while the die are still part of an uncut wafer, the only package to be created or assembled in this manner.  WLPs are array packages by nature, but since all the solder balls or bumps then must fit beneath the die itself, this limits the number of I/O which is on these packages.

The solution to this is the Reconfigured or Fan-out wafer-level packages (Fan-out WLP), for which the available surface available for I/O interface to the PCB is expanded beyond the perimeter of the die by virtue of a backside overmold.  All these processes are done on an uncut wafer, so that manufacturing efficiencies are maximized.

Like the Fan-in QFN, demand for both the WLP and the Fan-out WLP are on the rise.  This is displayed in Table 2.

Table 2 Fan-Out WLP

More Information

More information on these array package solutions can be found in New Venture Research’s latest published report, The Array IC Packaging Market. To find out more about this and other reports on IC packaging, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: 1-(408) 244-1100, or Sandra Winkler at slwinkler@newventureresearch.com, Tel: 1-(650) 299-9365.  See newventureresearch.com for information on all the reports from NVR.

Itty bitty computers, smart phones, ipods, and more – these “must have” small electronic devices that Apple Computer and other companies have popularized, are forcing the hand of IC package designers to shrink the package to fit within these little hand-held gadgets.

Shrinking the package can be a challenge, as is routing these devices to a PCB.  Creative package designs, such as stacked packages, SiPs, and interconnection methods of through silicon vias (TSVs) are all being put into play to achieve a small footprint, enhanced electrical performance, while consuming less battery power.  Information on those technologies can be found in New Venture Research’s Advanced IC Packaging, Technologies, Materials, and Markets, 2012 Edition.

Package Pitch

Another method of reducing the form factor and reduced signal length is to reduce the package pitch, or the distance between the center of one second-level interconnect to the other as the interconnect to the printed circuit board (PCB).  The package pitch of a device, combined with the I/O count, will determine the size of a package substrate or leadframe, the test socket size, and the footprint of the device on a PCB.

Reducing the pitch on an IC package often results in smaller solder balls on an array package, and will require that the electrical traces to the package on the PCB be closer together.

When a package pitch is altered, this will in turn have an effect on the PCB layout, the solder ball size where applicable and volume of solder paste, the test socket and DUT board, and all the parts used to make the package itself.

When combining the total packages together, the pitch of0.4 mmhas the largest growth of all the pitch sizes, while the 0.5-mm pitch comprises the largest single package pitch. Figure 1 displays the percentages of these pitches for the years 2012 versus 2017.

Figure 1 Total IC Package Pitch Forecast, 2012 vs. 2017

In New Venture Research’s newly published report, IC Package Pitch, Leadframe Plating, and Substrate Markets, IC package pitch data is presented by the major packaging families: DIP, SOT, SO, TSOP, DFN, CC, QFP, QFN, PGA, BGA, FBGA, and WLP, and by I/O count range: 4–18, 20–32, 34–100, 104–304, 308–999, and 1,000+.  Written, by Sandra L. Winkler, Senior Analyst, New Venture Research.

For more information, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: 1-(408) 244-1100, or Sandra Winkler at slwinkler@newventureresearch.com, Tel: 1-(650) 299-9365.  See newventureresearch.com for information on all the reports from NVR.

After 2009 being the worst depression since the Great Depression in the 1930’s through the mid-1940’s, the integrated circuit (IC) industry had a boom in the second half of 2010. 2011 began well on the heels of this boom, but a slowdown in the market in the second half of that year caused a negative growth rate, a pattern that repeated in 2012. The inventory corrections in these two years did not alter the fact that both 2011 and 2012 still had near-record-breaking unit and revenue figures. And of course the growth rates of 2010, with revenue growing 40 percent over 2009 and units 35.5 percent, were not sustainable.

Sales of tablets, smart phones, and automobiles are going well, and they are carrying the rest of the economy forward into recovery. Apple Computer had one blockbuster product after another, with the iPod, iPad, and iPhone. Apple, once the most valuable company in the world, is now number two behind Samsung. Producing portable electronic gadgets that connect people electronically with the world around them is clearly a good business model. Even in the depths of the recession of 2009, electronic gadgets that connected people via the Internet and sold for under $400 did well.

IC Revenue

Figure 1 illustrates IC revenue growth for the entire IC chip market. Revenue growth will be a steady increase through2017, asimilar trend to unit growth, and will have a 5.2 percent CAGR. The packaging revenue percent of IC revenue is shown at the bottom of this figure. The packaging revenue percent of IC revenue is displayed as well. Though it varies greatly by device type, overall packaging consumes slightly more than 15 percent of the total chip revenue and will rise to slightly more than 16 percent.

Figure 2  IC and Packaging Revenue Forecast and Percent of Packaging of Total, 2011—2017

For more in depth forecasts on IC packaging, please refer to New Venture Research’s newly published report, The Worldwide IC Packaging Market, 2013 Edition.  This report presents forecasts for each semiconductor product type, and segments these products by package family and I/O count range. Packaging revenue figures are displayed for each segment, based on prices charged in the outsourced assembly and test (OSAT) market. The package families are then rolled up by I/O count and semiconductor product. In doing so, the report generates the total value of the IC packaging industry.

Next, the report presents NVR’s continuing, extensive coverage of the OSAT market. OSATs will continue to assume a larger share of the world’s IC packaging business. The report breaks the OSAT market down by package families and major product categories providing units and revenue for each category. To further assess this group of companies, the report profiles the activities of the world’s largest OSAT companies and the packages they offer.

For more information on how to obtain this report, please contact Karen Williams at kwilliams@newventureresearch.com, Tel: (408) 244-1100.  Or, Sandra Winkler at slwinkler@newventureresearch.com, (650) 299-9365.

OSAT, or outsourced assembly and test, companies are businesses which offer integrated circuit (IC) packaging services on the open market, rather than being captive to the manufacturer of the die.  Thus they are a subset of the total worldwide IC packaging market, as much of the IC package assembly is still performed in-house at the fab which created the IC, the integrated semiconductor manufacturer (ISM).

Fabless and ISMs alike utilize the services of OSATs. Companies with their own packaging facilities use OSAT companies for work beyond the capacity of their own packaging plants and/or for specialty packaging. These OSAT companies are the “tail end of the whip”—it takes the brunt of swings in the semiconductor market. When the economy is down, semiconductor manufacturers will fill up their own packaging plants before contracting the work out to the OSAT companies, who can then be left with less work. Conversely, when the market is up, the OSAT firms’ plants are filled to overflowing. The result is that the OSATs can have an accentuated view of the swings in the semiconductor market.

The OSAT companies are in a position to invest in cutting edge packaging technologies, which the research and development dollars required for this effort being spread around many ISM and fabless companies.  Thus the OSATs are consuming a larger percentage of the overall worldwide IC packaging market over time.  Table 1 illustrates the percentage of the total IC package assembly market which is garnished by the OSAT companies, as based on New Venture Research’s report, The Worldwide IC Packaging Market, 2013 Edition.

Table 1 OSAT Percentage of the Total Worldwide IC Packaging Market

Successful OSAT companies seem to have the following three elements in common:

•    A broad and complete portfolio of packages and services

•    Close relations with the major wafer foundry companies and IDMs

•    An extremely lean cost structure

Over the last decade, numerous companies have tried to specialize in a few, specific types of packages. Many have failed. Although semiconductor companies want to use packaging foundries, they want to be able to go to just one or two companies for all of their packaging needs. This means that a packaging company must be prepared to assemble vast quantities of SOs—or even DIPs—at competitive prices. Approximately 42 percent of all packages assembled are DIPs, SOTs, SOs, and TSOPs! A broad portfolio of packages is a must.

Strategies of the Top Ten OSAT Companies

There are approximately 60 OSAT companies around the world competing for the outsourced package assembly dollars. Strategies vary, with some companies specializing in assembling multitudes of smaller packages, as is Carsem’s strategy, and others clamoring for the higher-value-added packages, such as 3-D solutions, FBGAs, BGAs, and the like. Amkor, ASE, SPIL, and STATS ChipPAC fall into this latter category.

How does each company position itself?

ASE, Inc.

ASE is the top OSAT company in terms of revenue. The company offers a broad spectrum of packages to fit a variety of needs, offering a one-stop shop for services. Though it assembles lower-end packages, ASE’s main focus and support is on the top-dollar value-added packages that bring more to the bottom line. Being vertically oriented to include package substrates in its product portfolio gives ASE a competitive edge in the array package business.

Amkor Technology

Founded in 1968, Amkor pioneered the outsourcing of IC assembly and test and is now a strategic manufacturing partner for more than 200 of the world’s leading semiconductor companies and electronics OEMs. A key Amkor strategy is to provide customers with innovative microelectronics assembly and test solutions to their challenging advanced packaging problems.

Amkor’s customers enjoy time-to-market benefits when they work with Amkor in an alpha customer engagement for the development of new package solutions to meet a device’s product requirements.

Amkor has built relationships with a number of system design companies to better understand long-term interconnect and packaging performance requirements. In many cases, such as for package on package (PoP) design, Amkor has active co-development projects with system design companies to enable developing PoP solutions that address system and device integration requirements.

Siliconware Precision Industries Co., Ltd. (SPIL)

SPIL offers a variety of packages within its portfolio, but focuses mainly on those with high growth rates for handheld electronics: QFN and MCP solutions, which include stacked packages and SiPs. SPIL ramped up its package and service options approximately seven years ago, rapidly moving to higher revenue earnings. Wafer bumping, final test, and drop shipment became part of its service portfolio.

STATS ChipPAC, Ltd.

STATS ChipPAC is a merger of STATS, which had a focus on final test, and ChipPAC, a package assembly company. The merger, approximately six or seven years ago, enabled provision of complete back-end services. The company included wafer bumping as a service two or three years ago, thus completing its flip chip line. It offers a host of QFN, FBGA, and MCP solutions (stacked packages, SiPs) that cater to the handheld communications market, which constitutes a majority of its package assembly revenue.

Powertech Technology, Inc.

Powertech is a more recent entrant into the package assembly business, entering in 1997. The company assembles a large number of MCPs, and focuses on packaging memory devices. Package assembly is all performed inChina. As with STATS ChipPAC, final test is a large part of its business.

Signetics

Signetics offers a number of array packages, in both wire bond and flip chip formats. The company also offers SO, QFN, QFP, and MCP solutions to round out its offerings. Its portfolio is not as broad as those of the top leaders, and is focused on the top competing packages rather than being a complete mix of all packages, which would include DIPs, TSOPs, CCs, DFNs, and WLPs. The company aims its products toward cell phones and consumer markets, flip chip products for networking, and graphics applications.

Carsem

Carsem’s specialty is meeting the tight tolerances of very small packages, and it offers numerous SOs within its package portfolio. Carsem also packages MEMS chips, which are coupled with ICs and have more complicated packaging issues in relation to ICs. The company produces a huge volume of assembly output, plus a full range of turnkey test services for RF, mixed signal, analog, digital, and power devices. It caters to the automotive, telecom, computer, and consumer electronics industries.

United Test and Assembly Center, Ltd. (UTAC)

UTAC offers a wide mix of package solutions, covering nearly all major package categories. The company offers semiconductor assembly and testing services for a broad range of integrated circuits, including mixed signal, analog, and memory, areas for which units are in high volume.

Unisem

Unisem also offers a broad mix of package solutions. The company’s turnkey services include design, assembly, test, failure analysis, and electrical and thermal characterization. Wafer bumping is also offered for its flip chip packages. The company also packages some MEMS devices.

JiangsuChangjiang Electronic Technology Co., Ltd.

Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET) performs package assembly for both discrete semiconductor devices and ICs. Only its IC packaging figures were taken into account within this report.

The company packages analog, power, RF, MPU, baseband, and power amplifier modules for the smart phone and tablet markets.

What Makes an OSAT Company Successful?

Success lies in having a complete package portfolio, rather than just a narrow range of a few package solutions. This broad spectrum grabs the higher revenue packages—SiPs, stacked packages, FBGAs, BGAs, etc.—as well as the multitudes of smaller packages such as QFN, SO, and the like. The smaller, lower I/O packages, in demand at high volumes in any economy, are used to package a multitude of analog and simple logic chips.

Right now handheld electronic gadgets are all the rage, so having a portfolio of packages aimed at these consumer electronics makes a lot of sense. These include stacked packages and SiPs. Flip chip and through-silicon vias (TSVs), found in the portfolios of the higher performing OSATs, offer advanced performance at a reduced size and also yield increased profits for the OSAT. The leading OSATs push the leading edge, and consider package development critical. They are aggressive at pursuing the top customers for volume production of higher revenue packages.

The leading OSATs offer test and turnkey services. The more complete the list of services that can be offered to meet all of a customer’s needs, the more successful the company. One-stop shopping helps both the customer and the OSAT company’s bottom line.

Prepared by Sandra L. Winkler, Senior Analyst, New Venture Research, newventureresearch.com; slwinkler@newventureresearch.com

The electronics manufacturing market is big – global assembly of printed circuit boards exceeded $1 trillion last year. Given such a vast marketplace, there are numerous opportunities for companies to specialize in one or another technology. Embedded computing is one such technology with a great deal of promise.

The merchant embedded computing (MEC) market is a specialized market within the larger electronics assembly marketplace. It is a dynamic industry with advances occurring continuously, thanks to an energetic standards development effort. MEC modules and components are board-level computing systems and solutions, based on specifications controlled by a dozen or so standards organizations that have grown up along with the industry. There are literally hundreds of standards – either adopted or still under development – controlling the design and manufacture of embedded applications. There are also more than 200 companies worldwide developing and manufacturing products for the marketplace, with an additional 100 to 200 participating in the distribution and assembly of embedded computing boards and their components.

New Venture Research has been tracking the merchant embedding computing market for over 15 years. In our latest report, the Merchant Embedded Computing Market – 2013 Edition, we provide an historical analysis and forecasts of the embedded computing market, as well as our observations of market trends for the coming five years. Data is based on field user surveys and interviews by industry participants as well as our other reports related to electronics assembly. We analyze the overall market from three separate, but interrelated perspectives:

•    Applications – five application segments targeted by MEC companies

•    Bus Architectures – nine categories, based on the bus architecture and form factors of embedded boards and modules

•    Board Function – four functional design categories of board-level products

Sadly, any current analysis of today’s electronics marketplace must start with the recession of 2009 – a near-economic calamity often compared to the Great Depression of the 1930s. The recession left an indelible mark on virtually every aspect of the global economy, not least the electronics assembly markets, including the market for embedded computing. Figure 1 shows the impact of the economic downturn on the MEC industry. In 2009, there was an abrupt and significant reversal in the growth rate as well as total revenues of the MEC market. The pain was felt in virtually every segment of the MEC market. Yet, seen from a wider perspective, the “Great Recession” was little more than a blip in a history of consistent growth by the industry. Despite the severity of the downturn, by 2012 the market had fully recovered in terms of total market size, and seemingly in momentum. Moreover, the MEC market is projected to continue growing well into the future, according to our research.

One reason for our optimism is based on the nature of the MEC industry. Thanks to the continuous evolution of old standards into new, and more advanced ones, the manufacturers of embedded computing modules and components are constantly working at the leading-edge of technology, providing to customers products that ultimately save them money. Ivan Straznicky, a Technical Fellow at Curtiss-Wright Controls Defense Systems, a long-time player in the merchant embedded computing market, points out that today’s merchant vendors can take advantage of the opportunity of “relieving the pain of our customers.” According to Straznicky, ‘Whereas in the past, they would have been tempted to build these components themselves, they now come to us because we have ready-made solutions that have been developed across multiple customers and been field-proven.” This is both the benefit and the promise of embedded computing.

Figure 1 MEC Industry Revenues ($M), 2003–2012

Positive Trends

There are a number of market trends that point toward a growing MEC market which include:

•    Purchasing by large sectors of the economy has picked up for MEC products, as telecommunications companies, industrial automation companies and government (particularly in the defense industry) are spending on repairing and replacing equipment that depend on embedded computing devices. Such maintenance work all but stopped during the recession, so pent-up demand is helping drive the market.

•    The transition toward digital communications, as well as skyrocketing traffic, is driving telecommunications carriers to rapidly upgrade their networks and private enterprise to increasingly move toward IP and data communications products. The MEC industry is well placed to take advantage of this transition.

•    Next-generation, high-integration silicon is enabling manufacturers to design board-level systems with capabilities not possible even five or six years ago. Improvements include lower energy consumption and very high-speed serial bus interconnects, all within small form factors. Embedded computing vendors are tightly focused on leading-edge technologies and board architectures, which will place them at the forefront of emerging markets in the coming years.

Microprocessor manufacturers, particularly Intel, continue to raise the bar with ever greater integration and more powerful chips, and as Jim Renehan, Director of Marketing at Gainesville, Georgia-based Trenton Systems points out, there is a need among standards to move up the “food-chain” to provide more capability for boards and plug-in cards.

MEC vendors face competition from other electronics sectors, as well, including the electronics manufacturing services (EMS) industry. (NVR tracks the EMS market in a companion report, The Worldwide Electronics Manufacturing Services Market).  Both industries depend on sales to OEMs and to government prime contractors. EMS vendors have an advantage in selling products in large numbers at low cost. Many MEC vendors, on the other hand, are small and specialized in niche markets. Their products are, by nature, customized and sold in small quantities. But the rewards in such a business model can be high, as the vendors can act quickly and build to specifications not possible by EMS competitors.

Some segments of the MEC industry have fared better than others as the market has emerged from the downturn, and in the following sections, we analyze the issues and opportunities for each of the major market sectors covered by our report.

Application Markets

The MEC market consists of four leading application markets – communications, industrial automation, medical, and military/aerospace – and an “other” category that includes a number of vertical markets, such as transportation, security, surveillance, point-of-sale/kiosk applications, etc.

These application markets tend to have very specific product requirements that differentiate them from one another, as well as from other electronics assembly market segments, such as PCs and the general purpose embedded electronics markets. Requirements include operating in harsh environmental conditions of temperature, humidity, or vibration; greater reliability and security; and specific real-time computing functionality. Hence, the market leaders, competitive forces, growth rates and size of the different application segments vary widely.

Figure 2 presents a top-level analysis of the MEC market from the point of view of the five application market segments for 2012. Prior to the industry downturn, the Communications Application market was the largest single market segment. However, general Industrial Automation Applications have made a stronger comeback than has been seen in the telecommunications sector and, by 2012, had become the largest and fastest growing MEC market.

The growth of the Industrial Automation Application market – “Big Data,” as Trenton Systems’ Jim Renehan refers to it – is at least partially a function of corporations around the world upgrading their circa-2007 systems with new energy-efficient systems. It is claimed that these new technologies can enable users to replace 10 servers with one new multicore server and allow an energy payback in less than 18 months. Other advances include large increases in the ability to move massive amounts of data in and out of systems, requiring interconnect speeds to grow from 1 Gbps today to 10 and 40 Gbps. This is good news for MEC communication suppliers, as well as industrial manufacturers.

Figure 2 MEC Industry Applications by Percent, 2012

Over the next five years, we expect this trend to continue. While the Communications Application market will grow at a pace equal with the overall market, Industrial Automation products will outpace communications, and will account for more than 1/3 of the total market by 2017.

The Medical Applications market segment was also hit hard by the financial crisis, which slowed MEC-based purchases of large equipment considerably. Unlike other manufacturing sectors, which have begun to replace and upgrade equipment, new spending in the medical segment is still being depressed, in part due to uncertainty in the United States about the forthcoming changes in the national healthcare system. Consequently, we do not expect the Medical Applications market to grow as quickly as other market segments.

The Military and Aerospace Applications market suffered in much the same way as the Industrial Automation market. And it has rebounded for much the same reason. NVR expects that various challenges of providing to the mil/aero market will slow its growth rate, somewhat. Growth in this market is closely tied to politics and to the security issues facing all defense-related markets, and these challenges will impact the short-term growth rates of the MEC Mil/Aero Applications market.

Even so, Michael Macpherson, VP of Strategic Planning at Curtiss-Wright Controls Defense Systems, points out that, overall, the global picture for this market segment looks quite healthy. Curtiss-Wright Controls, based in Charlotte, North Carolina, is a leading competitor in the military and aerospace market segment. From Macpherson’s point of view, it has been primarily in the U.S. where the market has some constraints. He specifically points to the debates over the budget and sequestration as having put pressure on the “top-line of the defense market.” As a consequence, there may not be quite as many of the multi-billion-dollar programs. “But we do the electronics,” Macpherson notes. “And while there may not be as many new, big programs, the fact that they are still upgrading and doing service life extension for existing platforms means they are still upgrading the electronics, and that is good for us.”

Rodger Hosking, a VP and one of the founders of Pentek, Inc., a New Jersey-based merchant embedded computing vendor that also focuses on government and military markets, agrees with that assessment. One of the drivers of this market, he points out, is that government organizations are faced with maintenance costs of older systems that can be replaced by newer systems with “one tenth of the cost, one tenth the power dissipation and one hundred times the performance. So, you look at the economics as well as the strategic advantages of some new technology, and it’s quite a simple equation for a government electronics customer to justify upgrading or replacing older equipment.”

Bus Architecture Markets

Market penetration by the various embedded computing bus architectures is driven as much by technology as it is by market forces. The nine bus architecture categories defined in our report are as follows:

•          PCI

•          CompactPCI

•          AdvancedTCA (ATCA)

•          VMEbus

•          PMC

•          AdvancedMC (AMC) and MicroTCA

•          PC/104 and its variants, plus EPIC, EBX and motherboards (ATX and ITX)

•          COM and COM Express

•          Other

Each MEC bus architecture has a different rate of adoption depending on the needs of individual application segments. Some are older parallel-bus technologies and nearing their end-of-life, as is the case for PCI-based buses, specifically the PCI and CompactPCI architectures. CompactPCI (cPCI) has historically captured the largest share of the MEC market, but this is changing, as PCI architecture market shares are rapidly shrinking. Figure 3 shows that cPCI was the largest single bus architecture segment in 2012. NVR expects that within two years, its market share will drop below that of VMEbus – however, not necessarily owing to any great growth by the latter segment. Also, an “old” bus architecture, VMEbus standards and products have changed and adapted to the advances in technology and consequently will remain a significant product segment. Helping VMEbus products to stay competitive is the fact that this architecture is specifically designed for extreme environments, a design feature that makes this an ideal product for many industrial automation applications and especially for mil/aero applications.

Yet, VMEbus will grow only more or less equally to the overall market, while the big winners for the future are products driving the industry toward higher integration in smaller form factors. This trend is reflected in the growth rates of the Computer-on-Module (COM) bus architecture. This technology will grow at double-digit rates between 2012 and 2017, largely because it is enabling vendors to create complete systems on a highly integrated single board. PC/104 and its variants are also small form factor architectures, but are not as trendy as COM.

Looking to the future, though, if you had to describe the most significant trend in the evolution of MEC architectures, it can be pared down to a single word: “Faster,” says Todd Wynia, VP of Planning and Development at Emerson Network Power Embedded Computing. “The industry has shifted away from bus-based architectures to a fabric-based industry,” he says. “Instead of being the VMEbus or compactPCI of the past, it’s now Ethernet-based backplanes for architectures like ATCA or the evolution of compactPCI or VPX – all fabric-based interfaces. And the evolution of those interfaces is ever-faster.”

In keeping with that evolution, we expect to see a rapid expansion of AdvancedTCA, as well as AdvancedMC bus architectures. Both of these form factors were originally developed for telecommunications applications, but they have since expanded into industrial automation markets and are consequently experiencing high growth rates. AdvancedMC is particularly worth watching. The AMC specification was only adopted in 2005, yet we expect that it will capture nearly 8% of the total MEC market by 2017.

New bus structures are continuously being developed by merchant vendors. Basing their design and manufacturing on existing standards and on new specifications being developed by the standards organizations, the vendors sell a bewildering array of off-the-shelf embedded board designs to OEMs and even end-users. Moreover, most companies are willing to develop custom architectures based on their existing product lines. This constant innovation serves to strengthen the MEC industry and at the same time fend off competition from EMS vendors. High volume is not necessarily the name of this game; rather it is innovation, customization and optimization that will drive the MEC market through the next decade.

Figure 3 MEC Bus Architectures by Percent, 2012

Board Function Markets

The MEC industry can also be categorized according to the functional design of embedded boards. NVR identifies four board function categories: single-board computers (SBCs), digital signal processor boards (DSPs), I/O boards, and Other board functions. The last category incorporates a huge number of diverse and specific functions, many of which are custom designs, including switchboards, chassis, backplanes, and system integration devices. The MEC board function markets are presented in Figure 4 providing market share of each functional category for 2012.

In some applications I/O boards are proliferating and are customized to the wide spectrum of I/O functions that different applications use. Other board functions are also proliferating, mostly owing to a growing demand for custom products. But the real story for MEC board functions is a persistent shift toward single board computers. MEC vendors are more and more integrating all of the electronic components and functionality into SBCs, creating complete systems. (This trend goes hand in hand with the growth of COM bus architecture, which is, by definition, a SBC board function.) Leading manufacturers, like GE Intelligent Platforms exemplify this trend. Based in Charlottesville, Virginia, GE considers single board computers as increasingly significant for its product line. According to Ian McMurray, speaking for the embedded computing group, SBCs are at the heart of GE Intelligent Platform’s military/aerospace business, incorporating an extensive range of component products, including microprocessors, sensor processing systems, video processing platforms, image processing technology and highly rugged routers and switches.

Increasing integration onto the SBC platform has always been a characteristic of this market segment, and it goes hand-in-hand with the evolution of bus architecture technology. The key elements driving this trend – processors, fabrics and integration – are leading increasingly toward advanced fabric-centric architectures, such as VPX, which McMurray notes has become the architecture of choice for new military programs at GE Intelligent Platforms. Moreover, as SBCs integrate and incorporate ever more of digital signal processing and graphics and I/O functionality, the need for separate DSPs and I/O boards decreases, and leads to growing demand for single board products like the COM Express form factor. Thus, already accounting for more than half the total MEC market in 2012, NVR projects that the SBC market segment will continue to expand its market share of the total MEC market over the next five years and beyond.

Figure 4 MEC Board Functions by Percent, 2012

Conclusions

Throughout this discussion, we have touched only lightly on the thing that gives meaning to the merchant embedded computing market: the active, dynamic standards process. Despite a bewildering array of products and designs, the products that drive the MEC market are themselves driven by a relatively few organizations that bring together (sometimes fierce) competitors to work collectively to develop open specifications that help everyone – manufacturers and customers alike. From the earliest consortiums – such as VITA, PCI-SIG and PICMG – to the most recent – SFF-SIG and SGeT – these organizations empower manufacturers to concentrate, not on basic form factors and connectors, but on building the best mousetrap for the application.

Significant changes are happening in the MEC marketplace and in the electronics industry, in general. Along with the evolution of technologies, such as the shift from parallel to serial and from simple buses to fabric-based architectures, the standards organizations are constantly evolving their standards to keep pace. As Moore’s Law continues to be demonstrated by ever more powerful chips, applications once needing discrete chips for separate tasks are being integrated into single, more densely packed chips – and new standards specifications will make it possible to integrate those chips into embedded designs. The challenges raised by decreasing size and increasing performance cannot effectively be addressed by individual companies. It is the PICMGs, VITAs and SFF-SIGs that will help speed these trends. It is these organizations that are helping define the future of embedded computing by advancing the technologies incorporated in standards specifications.

These trends are altering the MEC board market at an accelerated pace. Not only will much of today’s separate chip functionality get subsumed into a single chip design, but also the computational power and functionality of single-board computers will skyrocket. “There are always challenges to overcome, concludes Rodger Hosking of Pentek. “That’s what keeps us in business and it’s what keeps the industry going. The big driver is the silicon and component technology that we are all benefiting from in our lives. Everything that we are surrounded by – the electronics in our cars, mobile electronics, everything – is getting more powerful, smaller, less expensive.”

Jerry Watkins is a senior analyst with New Venture Research and has more than 20 years of experience in the field of market research and consulting.  Mr. Watkins has authored numerous syndicated reports in the telecommunications sector and more recently in the computing and merchant embedded computing industry.  He holds three university degrees including a B.A. in History and a M.A. in International Studies.

ECTC in Las Vegas

What happens in Las Vegas at ECTC doesn’t stay in Las Vegas, it is shared here.

This year’s ECTC, or electronics components technology conference, was held in Las Vegas’ Cosmopolitan, May 28—31^st, 2013.  Here are some conference statistics:

• Over 1,300 attendees, the highest attendance ever, from 26 countries
• 377 technical papers, presented in 36 oral and five interactive presentation sessions, including a student poster session
• 12 sessions focused on 3D/TSV, including several of the best attended sessions of the conference
• 16 professional development courses attended by over 300 participants
• 95 Technology Corner exhibitors – also a new record

In addition to the regular daytime sessions and courses, there were two special sessions on Tuesday, and three evening seminars that were all very well attended.

ECTC Special Session

• Chaired by Sam Karikalan of Broadcom Corporation on the collaboration between wafer foundries, OSATs, and materials and tool suppliers as the key to the success of next generation packaging

This ECTC special session on Tuesday morning included speakers Jerry Tzou of TSMC, David McCann of GLOBALFOUNDRIES, Kurt Huang of UMC, Jon Casey of IBM Corporation, and Herb Huang of SMIC, and was titled “The Role of Wafer Foundries in Next Generation Packaging”.  The main thrust of this was that collaborative development is critical, and that there must be a supply chain integration between foundry and OSAT to make 2.5- and 3-D integration come to life.  That is, there needs to be a blurring of lines between the parties involved, where everyone pitches to make it all happen, rather than the compartmentalizing the tasks as what happens now.  Packaging innovation is required to take place once the line and space lithographies drop to 90 nanometers (nm) and below, such as 2.5- and 3-D innovation.  Scaling can occur down to 7 nm, as foreseen at this time.

The three business models exist for 3-D interconnect:

• FEoL (front end of line)
• MEoL (middle end of line)
• BEoL (back end of line)

UMC was promoting an Open Eco-System, which is working for 2.5-D currently, and in the formulation mode for 3-D now.  Cost is an issue for these interconnect models currently, and combined efforts on EDA tools and reliability testing would help all participants.

Creating a heterogeneous 3-D integrated stacked package will offer huge performance benefits, but will be a major challenge with tight integration requirements as well.  Power management will be critical in development of these powerful packages.  Dissipating the heat is even more critical in handheld devices, as production of 6 watts is too hot an item to hold in one’s hand. At this rate, a 4K video would operate at 40GHz, and the battery would be used up in about ten minutes.

An idea to handle the heat is to place the hottest chip on top, and use fine micro-fluidic cooling for cooling the entire device structure.

The purpose in creating these complex packaging structures is primarily for bandwidth for small phones and tablets, but also for computing power.  Future markets for these package innovations include smart wearables such as small watches and glasses.  Streaming videos with a crisp image will also be possible with the extra bandwidth.

ECTC Panel Session

• Co-chaired by Ricky Lee of the Hong Kong University of Science and Technology and Kouchi Zhang of TU Delft & Philips Lighting on the growing market of LED for solid-state lighting

Speakers include Ling Wu of China Solid State lighting Alliance, Mark McClear of Cree Components, Ron Bonne of Philips Lumileds, Nils Ekamp of TNO, and Michael McLaughlin of Yole Development.  This session occurred on Tuesday May 28^th.

ECTC Plenary Session

• Chaired by Lou Nicholls of Amkor Technologies on the “Packaging Challenges Across the Wireless Market Supply Chain”

Speakers included on the Wednesday evening session were Timo Hentonen of Nokia, Steve Bezuk of Qualcomm Technologies, Waite Warren of RFMD, Roger St. Amand of Amkor Technology, and SoonJin Cho of SEMCO.

Handheld devices in the wireless market, such as cellular telephones, ultrabooks, and more, are collectively experiencing an 18 percent compound annual growth rate (CAGR).  Challenges and issues include:

• Thermal – get the heat out
• Get more functionality into the smallest form factor possible, and more features = more power = more heat
• The next pitch node
• Materials and processes, such a low-k, lower k dielectrics, low CTE resin, and glass cloth.  Thin materials needed but need to be stiff to address warpage issues.
• Mechanical, including ultra-thin of <150 µm, CTE, warpage
• Electrical, including signal integrity
• Supply chain roadmaps and collaborative efforts to ensure seamless integration
• Higher data rate / more bandwidth. Need to send and receive at the same time, and the need for Microshield™.
• Routing density and embedding passive devices in the 2012 – 2013 time frame, and active devices in 2014 and 2015.  Challenges will include via to pad alignment, reliability (crack and alignment), low profile but high capacitance, and substrate yield.
• The move from a cored substrate to coreless to achieve a thinner substrate and thus package height (1.1 mm to 0.6 mm).  Minimize thickness variation to minimize warpage.
• Bump volume and volume uniformity
• µbump mounting in the future
• Interposer thinness and metal count layers are also challenges.

The handset thickness is going down, to 6 mm in the case of the latest Nokia phone.  The PoP solution contains a memory and processor, and is thinner than a penny, which must stay flat.  The supply chain for a product must be coordinated with for two years prior to product launch to ensure that the product will come together in time for market.

Copper pillars allow for a finer pitch, which are connected via thermal compression.  By moving to finer pitch, the package design can move from a full array pattern to a peripheral array, thus reducing the metal layers on the substrate from four to two, reducing costs. Warpage can be controlled by applying pressure to the top of the package during the heat cycle of this process.

When a second die is attached to a package substrate on the underside of the package using flip chip interconnection for a Possum™ style package, warpage is controlled by employing a 0-2-2 substrate.

Warpage is controlled on bare die on the corners by putting a lid on the top of this die.

The next issue for this market in a low cost interposer (LCI).  Currently interposers are predominantly silicon, but laminate and glass are being explored.  A supply chain must be created for these materials if they are to become viable alternatives as interposers.

CPMT Seminar

• Co-chaired by Kishio Yokouchi of Fujitsu Interconnect Technologies Ltd. and Venky Sundaram of the Georgia Institute of Technology on advanced low loss dielectric materials for high frequency and high bandwidth applications

Speakers at the Thursday evening seminar include Yuka Suzuki of Zeon Corporation, Yasuyuki Mizuno of Tsukuba Research Laboratory, Hitachi Chemical Co., Ltd., Shin Teraki of NAMICS Corporation, and Hirohisa Narahashi of The Research Institute for Bioscience Products & Fine Chemical, Ajinomoto Co., Inc.

Modeling Special Session

• Co-chaired by Yong Liu of Fairchild Semiconductor and Dan Oh of Altera on “Modeling and Simulation Challenges in 3D Systems”

Luncheon Keynote

The ECTC Keynote Speaker, Dr. Chris Welty from IBM, brought his vision and experience on solving engineering problems in a very entertaining presentation on the design and competition of the Watson supercomputer in the Jeopardy! TV game show during Wednesday’s luncheon.  Watson was designed to compete against former star players on Jeopardy! without having access to the Internet, and had to compute an answer to the question given within only seconds.  The size of Watson dictated that this supercomputer, the size of a room, had to sit outside the televised viewing room, and not in the actual viewing room on a chair.  As Dr. Welty stated, Watson, in technical terms, sucked at the game.  The hilarious answers provided by Watson to the questions stemmed from a lack of being able to understand the actual questions being asked, which would include an understanding of nouns, verbs, etc.  Watson’s “brain” did word searches in its database and came up with answers based on the frequency of how often a word was mentioned in news articles.  Thus the actual question was not answered correctly, and reprogramming of Watson had to occur for it to have the ability to recognize the actual question. Since this was an engineering conference, I guess the concept of trying to teach Watson how to understand the question fit right in…

Corporate sponsors, including the gala sponsors, include Nanium, Amkor, DOW Electronic Materials, AMAT, Microsoft and STATSChipPAC.  The luncheon and program sponsors include Corning, ASE, GLOBALFOUNDRIES, NCAP, Invensas and HD MicroSystems.

Photos taken at the conference are posted on Flickr: http://www.flickr.com/photos/38916807@N07/sets/72157633891833244/

Next year’s conference will be held May 27-30, 2014, at the Walt Disney World Swan & Dolphin Hotel in Lake Buena Vista,Florida,USA.

Selected Images from the ETCT Conference (see PDF file)

The Internet has altered the ways in which individuals and businesses worldwide function, communicate, and connect. The hardware that enables this, and the need for more bandwidth to support it, are driving technological advances in many ways. Much progress has been made in front-end manufacturing, and much of the current focus on increasing Internet speeds is on the “back end,” or the packaging end of the chip-making process, known as “More than Moore,” after Moore’s Law.

A number of packaging solutions are designed to enhance chip performance, while at the same time maintaining a space-constrained footprint. These package solutions and options include:

•    Stacked packages

•    Through-silicon vias (TSVs), including 3-D and 2.5-D

•    System in package (SiP)

•    Fan-in QFN packages

•    WLPs, including fan-out WLPs

•    Flip chip interconnection

Stacked packages stack the die vertically for close coupling of the die while consuming very little space on the PCB. This packaging solution can be applied to a number of different IC packages, with the FBGA being prominent. Stacked packages have a 13.7 percent compound annual growth rate (CAGR) from 2011 through 2016.

Through-silicon vias (TSVs) are a newer form of interconnection, connecting the die in a stack either through the bulk silicon (3-D interconnection) or through a substrate or interposer within the stack (2.5-D).  TSVs that connect ICs together using these methods have enormous growth potential, and have begun to be produced in volume.

System in package (SiP) is a functional block, pulling devices needed for certain functions into a unit for close coupling for superior performance and space saving. Cell phones are the primary candidates for this technology.  SiPs have a unit growth rate of 13 percent CAGR through 2012.

Fan-in QFNs extend the number of rows of leads from the usual one with a traditional QFN to two or three rows of leads. The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multirow, array-patterned package solution with a hole in the center, or fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. The resulting package is a high-density, leadframe array package. The fan-in QFN and fan-in QFP market will experience unit growth of 38.6 percent CAGR for the years 2011 through 2016.

Reconfigured or fan-out wafer-level packages were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-in WLPs will experience an 11.6 percent CAGR through 2016.

Flip chip is an interconnection style that “flips” the die upside down (or active side down) so that the circuitry faces the substrate. This requires putting bumps on the pads to make the electrical connectivity points protrude from the face of the chip. The bumps then carry the electrical signal in lieu of wire bonds. Because the entire face of the die is available for electrical connections, a higher number of I/O (input/output) signals can fit in a smaller footprint. Superior electrical performance can also be achieved due to the shorter electrical length and fewer parasitics. The use of flip chip becomes mandatory on any die with an I/O count so high that the pads cannot fit around the die perimeter. Flip chip is also used for some high-frequency RF devices. This technology, used in IC packages, will have unit growth of 12.6 percent CAGR through 2016.

Sandra L. Winkler is a Senior Industry Analyst with New Venture Research Corp. and has been writing and researching the semiconductor packaging industry for more than 20 years.  More information on these topics and others can be found on New Venture Research’s website at: www.newventureresearch.com/

The Wireless Mobility Assembly Markets – 2012 Edition report provides critical information on the electronics COGS manufacturing assembly.  For more information, see https://newventureresearch.com/wp-content/uploads/2012/11/mm12bro-rs.pdf