The Internet has altered the ways in which individuals and businesses worldwide function, communicate, and connect. The hardware that enables this, and the need for more bandwidth to support it, are driving technological advances in many ways. Much progress has been made in front-end manufacturing, and much of the current focus on increasing Internet speeds is on the “back end,” or the packaging end of the chip-making process, known as “More than Moore,” after Moore’s Law.

A number of packaging solutions are designed to enhance chip performance, while at the same time maintaining a space-constrained footprint. These package solutions and options include:

•    Stacked packages

•    Through-silicon vias (TSVs), including 3-D and 2.5-D

•    System in package (SiP)

•    Fan-in QFN packages

•    WLPs, including fan-out WLPs

•    Flip chip interconnection

Stacked packages stack the die vertically for close coupling of the die while consuming very little space on the PCB. This packaging solution can be applied to a number of different IC packages, with the FBGA being prominent. Stacked packages have a 13.7 percent compound annual growth rate (CAGR) from 2011 through 2016.

Through-silicon vias (TSVs) are a newer form of interconnection, connecting the die in a stack either through the bulk silicon (3-D interconnection) or through a substrate or interposer within the stack (2.5-D).  TSVs that connect ICs together using these methods have enormous growth potential, and have begun to be produced in volume.

System in package (SiP) is a functional block, pulling devices needed for certain functions into a unit for close coupling for superior performance and space saving. Cell phones are the primary candidates for this technology.  SiPs have a unit growth rate of 13 percent CAGR through 2012.

Fan-in QFNs extend the number of rows of leads from the usual one with a traditional QFN to two or three rows of leads. The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multirow, array-patterned package solution with a hole in the center, or fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. The resulting package is a high-density, leadframe array package. The fan-in QFN and fan-in QFP market will experience unit growth of 38.6 percent CAGR for the years 2011 through 2016.

Reconfigured or fan-out wafer-level packages were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-in WLPs will experience an 11.6 percent CAGR through 2016.

Flip chip is an interconnection style that “flips” the die upside down (or active side down) so that the circuitry faces the substrate. This requires putting bumps on the pads to make the electrical connectivity points protrude from the face of the chip. The bumps then carry the electrical signal in lieu of wire bonds. Because the entire face of the die is available for electrical connections, a higher number of I/O (input/output) signals can fit in a smaller footprint. Superior electrical performance can also be achieved due to the shorter electrical length and fewer parasitics. The use of flip chip becomes mandatory on any die with an I/O count so high that the pads cannot fit around the die perimeter. Flip chip is also used for some high-frequency RF devices. This technology, used in IC packages, will have unit growth of 12.6 percent CAGR through 2016.

Sandra L. Winkler is a Senior Industry Analyst with New Venture Research Corp. and has been writing and researching the semiconductor packaging industry for more than 20 years.  More information on these topics and others can be found on New Venture Research’s website at: